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rev 1.0/ aug. 2010 1 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 64gb flash H27UCG8T2M http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 2 H27UCG8T2M series 64gb (8192m x 8bit) nand flash document title 64gbit (8192 m x 8 bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. apr. 27. 2010 preliminary 1.0 finalize aug. 17. 2010 advanced http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 3 H27UCG8T2M series 64gb (8192m x 8bit) nand flash product feature open nand flash interface (onfi) 1.0 compliant supports only asynchronous interface multilevel cell(mlc) technology device size - 64 gbit = 4,096 blocks organization - page size : 8,640 bytes(8,192+448 bytes) - block size : 256 pages(2m+112k bytes) - plane size : 2,048 blocks - chip size : 2 planes (4,096 blocks) supply voltage - 3.3v device : vcc = 2.7 v ~ 3.6 v read time - random access (tr): 200 ? (max.) - sequential access : 20 ? (min.) write time - page program : 1600 ? (typ.) - block erase : 3.5 ? (typ.) package information - package type : vlga - chip count : sdp(1ce, single) = 1 stack - ball(pin) count : 52 ball - size : 14mm x 18mm x 1mm endurance: - 1,000 program/erase cycles - data retention: 10 years operating temperature: - 0c to +70c (commercial) - -25c to +85c (extended) - -4 0c to +85c (industrial) http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 4 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 1. summary description the product part no.h27ucg8t2yr-bc is a single 3.3v 64gbit nand flash memory. the device contains 2 planes in a sin - gle die. each plane is made up of the 2,048 blocks. each block consists of 256 programmable pages. each page contains 8,640 bytes. the pages are subdivided into an 8,192-byte main data storage area with a spare 448-byte district. page program operation can be performed in typical 1,600us, and a single block can be erased in typical 3.5ms. 1.1. product list table 1 part number density # of ce# and r/b# package device id H27UCG8T2Myr 64gb 1 52- lga ad-de-94-d2-04-43 http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 5 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 1.2. pin description note: a 0.1uf capacitor should be connected between the vcc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during pro gram and erase operations. pin name description i/o0-i/o7 data inputs/outputs the i/o pins is used to command latch cycle, address input cycle, and data in-out cycles during read / write operations. the i/o pins float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable this input activates the latching of the i/o inputs inside the address register on the rising edge of write enable (we#). ce# chip enable this input controls the selection of the device. when the device is busy, ce# low does not deselect the memory. the device goes into stand-by mode when ce# goes high during the device is in ready state. the ce# signal is ignored when device is in busy state, and will not enter standby mode even if the ce# goes high. we# write enable this input acts as clock to latch command, address an d data. the i/o inputs are latched on the rise edge of we#. re# read enable the re# input is the serial data-out control, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re# which also in crements the internal column address counter by one. wp# write protect the wp# pin, when low, provides a hardware protection against undesired write operations. hardware write protection is activated when the write protect pi n is low. in this condition modify operation do not start and the content of the memory is not altered. write protect pin is not latched by write enable to ensure the protection even during the power up phases. r/b# ready / busy the ready/busy output is an open drain pin that signals the state of the memory. vccq supply voltage for i/o buffer vssq ground for i/o buffer vcc supply voltage the vcc supplies the power for all the operations. (read, write, and erase). vss ground nc no connected http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 6 H27UCG8T2M series 64gb (8192m x 8bit) nand flash vcc vss wp# cle ale re# we# ce# i/o0~i/o7 r/b# vccq vssq pin diagram figure 1. pin diagram (sdp) http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 7 H27UCG8T2M series 64gb (8192m x 8bit) nand flash a b c d e f g h j k l m n oa ob oc od oe of nc nc nc nc nc nc nc re# nc nc vcc nc nc vcc nc io7 vcc io5 vss nc ale nc nc vccq nc nc vss nc io1 vss io3 wp# cle nc we# io2 nc vss io0 ce# nc r/b io6 nc io4 nc 8 7 6 5 4 3 2 1 0 nc nc nc nc vssq nc ball map(52-vlga) - raw nand pkg (single channel) http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 8 H27UCG8T2M series 64gb (8192m x 8bit) nand flash raw nand pkg (52-vlga) http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 9 H27UCG8T2M series 64gb (8192m x 8bit) nand flash x decoder address register ale cle ce# we# re# wp# command interface logic program/erase controller hv generation y decoder address register command register io buffer & latch x d e c o d e r nand flash memory array 1 device = (8,192 + 448) bytes x 256pages x 4096 blocks = 70,778,880 kbits data register & sense amp column decoder vcc vss global data buffer output driver a14-a33 a0-a13 i/o<7:0> 1.3. block diagram figure 2. block diagram http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 10 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 1.4. array organization figure 3. array organization 1.5. addressing notes: 1. l must be set to low. 2. the device ignores any additional address input cycle than required. 3. the address consists of column address (a0~a13), page address (a14 ~ a21), plane address (a22), and block address (a23 ~ the last address). bus cycle i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1 st cycle a0 a1 a2 a3 a4 a5 a6 a7 2 nd cycle a8 a9 a10 a11 a12 a13 l (1) l (1) 3 rd cycle a14 a15 a16 a17 a18 a19 a20 a21 4 th cycle a22 a23 a24 a25 a26 a27 a28 a29 5 th cycle a30 a31 a32 a33 l (1) l (1) l (1) l (1) http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 11 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 1.6. command set function 1 st cycle number of address cycles data input cycles 2 nd cycle number of address cycles data input cycles 3 rd cycle acceptable command during busy page read 00h 5 - 30h - - - no read for copy-back 00h 5 - 35h - - - no random data output 1) 05h 2 - e0h - - - no single/multi plane cache read 5) 31h - - - - - - no single/multi plane cache read end 5) 3fh - - - - - - no read id 90h 1 - - - - - no read status register 70h - - - - - - yes page pgm (start) / cache pgm 5) (end) 80h 5 yes 10h - - - no random data input 1) 85h 2 yes - - - - no copy-back pgm 85h 5 option 10h - - - no cache pgm (start) 5) 80h 5 yes 15h - - - no block erase 60h 3 - d0h - - - no reset ffh - - - - - yes multi plane page read 60h 3 - 60h 3 - 30h no multi plane cache read start 5) 6) 60h 3 - 60h 3 - 33h no multi plane read for copy-back 60h 3 - 60h 3 - 35h no multi plane block erase 60h 3 - 60h 3 - d0h no multi plane data output 1) 3) 00h 5 - 05h 2 - e0h no multi plane read status register 78h 3 - - - - - yes multi-plane read status register (legacy) 75h - - - ---yes multi plane page pgm / multi plane cache pgm (end) 80h 5 yes 11h~81h 2) 5 yes 10h no multi plane copy-back pgm 85h 5 option 11h~81h 2) 5 option 10h no multi plane cache pgm (start) 5) 80h 5 yes 11h~81h 2) 5 yes 15h no cache read enhanced 00h 5 - 31h - - - no multi-plane cache read enhanced 60h 3 - 60h 3 - 31h no http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 12 H27UCG8T2M series 64gb (8192m x 8bit) nand flash notes: 1. random data input/output must be performed in a selected page. 2. any command between 11h and 81h is prohibited except 70h, 78h, 75h and ffh. 3. multi plane random data-out must be used after multi plane read operations (multi plane page read, multi plane cache read and multi plane read for copy back). 4. do not change plane address order when using all multi plane operations. 5. all cache operation (cache program, cache read) is available only within a block. 6. it's possible to confirm the multi-plan e cache read first step using both 30h and 33h. caution: 1. any undefined command inputs are prohibited except for above command set. 2. multi plane page read, multi plane cache read, and mu lti plane read for copy-back must be used after multi plane pro grammed page, multi plane cache program, and multi plane copy-back program. 1.7. mode selection notes: 1. x can be v il or v ih . h = logic level high. l = logic level low. 2. wp# should be biased to cmos high or cmos low for stand-by mode. 3. we# and re# during read busy must be keep on high to prevent unplanned command/address/data input or to avert unintended data out. in this time, only reset, re ad status, and multi plane read status can be inputted to the device. cle ale ce# we# re# wp# mode h l l h x read mode command input l h l h x address input ( 5 cycles ) h l l h h write mode command input l h 1) l h h address input ( 5 cycles ) l l l h h data input l l 1) l h x sequential read and data output x x x h 3) h 3) x during read (busy) x x 1) x x x h during program (busy) x x x x x h during erase (busy) x x x x x l write protect x x h x x ov/vcc 2) stand-by http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 13 H27UCG8T2M series 64gb (8192m x 8bit) nand flash start block no = 0 read ffh check column 8192 of the 1 st page last block end entry bad block fail fail pass yes block no. = block no. + 1 pass no read ffh check col. 8192 of the last page 1.8. bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping. any bl ock where the 1st byte in the spare area of the first and last page does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table fo llowing the flowchart shown in flow chart 1. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment. flow chart 1. bad block management flow chart notes: 1. do not try to erase the detected bad blocks, because the bad block information will be lost. 2. do not perform program and erase operation in invalid block, it is impossible to guarantee the input data and to ensure that the function is normal. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 14 H27UCG8T2M series 64gb (8192m x 8bit) nand flash block a block b data data failure ffh ffh buffer memory controller 1 page st 1 page st nth page nth page (2) (3) 1.9. bad block replacement this device may have the invalid blocks when shipped from factory. an invalid block is one that contains one or more bad bits. over the lifetime of the device additional bad blocks may develop. in this case, the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. the failure of a page program operation does not affect the data in other pages in the same block. bad block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. refer to table 2 and figure 4 for the recommended procedur e to follow if an error occurs during an operation. table 2. block failure figure 4. block replacement notes: 1. an error occurs on nth page of th e block a during program or erase operation. 2. data in block a is copied to same location in block b which is valid block. 3. nth page of block a which is in controller buffer memory is copied into nth page of block b. 4. bad block table should be updated to prevent from erasing or programming block a. operation recommended procedure erase block replacement program block replacement read ecc http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 15 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2. electrical characteristics 2.1. valid blocks notes: 1. the 1st block is gu aranteed to be a valid block at the time of shipment. 2. this single device has a maximum of 96 invalid blocks. 3. invalid blocks are one that contains one or more bad bits. the device may contain bad blocks upon shipment. 2.2. absolute maximum rating notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to ab solute maximum rating conditio ns for extended periods may affect device reliability. refer also to the hynix sure program and other relevant quality documents. 2. minimum voltage may undershoot to -2v during transition and for less than 20ns during transitions. symbol min typ max unit valid block number n vb 4000 4096 blocks symbol parameter value unit min t a ambient operating temperature (commercial temperature range) 0 to 70 c ambient operating temperature (extended temperature range) -25 to 85 c ambient operating temperature (industrial temperature range) -40 to 85 c t bias temperature under bias -50 to 125 c t stg storage temperature -65 to 150 c v io input or output voltage -0.6 to 4.6 v v cc supply voltage -0.6 to 4.6 v http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 16 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.3. dc and operating characteristics parameter symbol test conditions hy27ucg8t2a unit 3.3v min typ max power on reset current i cc0 ffh command input after power on -- 50per device ma operating current read i cc1 t rc = t rc (min), ce#=v il , i out =0 ? --50 ma program i cc2 ---50 ma erase i cc3 ---50 ma stand-by current (ttl) i cc4 ce#=v ih , wp#=0v/v cc -- 1 ma stand-by current (cmos) i cc5 ce#=vcc-0.2, wp#=0v/v cc -1050 ua input leakage current i li v in =0 to v cc (max) -- 10 ua output leakage current i lo v out =0 to v cc(max) -- 10 ua input high voltage v ih - vccx0.8 - vcc+0.3 v input low voltage v il - -0.3 - 0.2x vcc v output high voltage v oh i oh =-400 ? 2.4 - - v output low voltage v ol i ol =2.1 ? --0.4v output low current (r/b#) i ol (r/b#) v ol =0.4v 810 - ma http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 17 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.4. ac test conditions notes: 1.these parameters are verified device characterization and are not 100% tested. 2.5. pin capacitance (t a =25c , f=1.0 ? ) 2.6. program/ read / erase characteristics notes: 1. typical value is measured at v cc =3.3v, t a =25 . not 100% tested. parameter value 2.7v vcc 3.6v input pulse levels 0 v to vcc input rise and fall times 5 ns input and output timing levels vcc /2 output load (2.7v-3.6v) 1 ttl gate and cl=50pf symbol parameter test condition min max unit c in input capacitance v in = 0v -10 pf c i/o input/output capacitance v in = 0v -10 pf parameter symbol min typ max unit program (following 10h) t prog - 1600 3500 us cache program (following 15h) t cbsyw -- - us multi plane program / multi plane cache program / multi plane copy-back program (following 11h) t dbsy -3 5 us cache read / multi plane cache read (following 31h/3fh) t cbsyr - 3 200 us block erase / multi plane block erase t bers -3.510 ms number of partial program cycles in the same page nop - - 1 cycles http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 18 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.7. ac timing characteristics parameter symbol 3.3v unit min max cle setup time t cls 12 ns cle hold time t clh 5ns ce# setup time t cs 20 ns ce# hold time t ch 5ns we# pulse width t wp 8ns ale setup time t als 10 ns ale hold time t alh 5ns data setup time t ds 10 ns data hold time t dh 5ns write cycle time t wc 20 ns we# high hold time t wh 10 ns data transfer from cell to register t r 200 us ale to re# delay t ar 10 ns cle to re# delay t clr 10 ns ready to re# low t rr 20 ns re# pulse width t rp 10 ns we# high to busy t wb 100 ns read cycle time t rc 20 ns re# access time t rea 16 ns re# high to output high z t rhz 100 ns ce# high to output high z t chz 50 ns re# high to output hold t rhoh 15 ns re# low to output hold t rloh 5ns re# or ce# high to output hold t coh 15 ns re# high hold time t reh 8ns we# high to re# low t whr 80 ns re# high to we# low t rhw 100 ns output high z to re# low t ir 0ns ce# low to re# low t cr 10 ns address to data loading time t ald 200 ns http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 19 H27UCG8T2M series 64gb (8192m x 8bit) nand flash notes: 1. if reset command (ffh) is written at ready state, the device goes into busy for maximum 5us. 2. program / erase enable operation: wp# high to we# high. program / erase disable operation: wp# low to we# high. 3. the transition of the corresponding control pins must occur only while we# is held low. 4. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. device resetting time (read/program/erase) t rst 20/30/500 us write protection time t ww 100 ns http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 20 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.8. status register coding 2.8.1. status register coding for 70h/78h command notes: 1. i/o0: this bit is only valid for program an d erase operations. during cache program operations, this bit is only valid when i/o5 is set to one. 2. i/o1: this bit is only valid for cache prog ram operations. this bit is not valid until after the second 15h command or the 10h command has been transferred in a cache program sequence. when cache program is not supported, this bit is not used. 3. i/o5: if set to one, then th ere is no array operation in progress. if cleared to zero, then there is a command being processed (i/o6 is cleared to zero) or an array operation in progress. when overlapped interleaved operations or cach e commands are not supported, this bit is not used. 4. i/o6: if set to one, then the device or inte rleaved address is ready for another command and all other bits in the status value are valid. if cleared to zero, then the last command issued is not yet complete and status register bits<5:0> are invalid value. when cache operations are in use, then this bit indicates whether another command can be accepted, and i/o5 indicates whether the last operation is complete. i/o page program block erase read cache read cache program coding 70h/ 78h 0 pass/ fail pass/ fail n/a n/a pass/ fail (n) n page pass : '0' fail : '1' 1 n/a n/a n/a n/a pass/ fail (n-1) n-1 page pass : '0' fail : '1' 2 n/a n/a n/a n/a n/a '0' 3 n/a n/a n/a n/a n/a '0' 4 n/a n/a n/a n/a n/a '0' 5 n/a n/a n/a ready / busy ready / busy ready / busy busy : '0' ready : '1' 6 ready / busy ready / busy ready / busy ready / busy ready / busy data cache ready / busy : '0' ready : '1' 7 write protect write protect write protect write protect write protect protected : '0' not protected : ' 1 ' http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 21 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.8.2. status register coding for 75h command 2.9. device identifier coding i/o page program block erase read cache read cache program coding 70h/ 78h 0 chip pass/ fail chip pass/ fail n/a n/a chip pass/ fail (n) n page pass : '0' fail : '1' 1 plane 0 pass/ fail plane 0 pass/ fail n/a n/a plane 0 pass/ fail (n) n page pass : '0' fail : '1' 2 plane 1 pass/ fail plane 1 pass/ fail n/a n/a plane 1 pass/ fail (n) n page pass : '0' fail : '1' 3 n/a n/a n/a n/a plane 0 pass/ fail (n-1) n page pass : '0' fail : '1' 4 n/a n/a n/a n/a plane 1 pass/ fail (n-1) n page pass : '0' fail : '1' 5 n/a n/a n/a ready / busy ready / busy ready / busy busy : '0' ready : '1' 6 ready / busy ready / busy ready / busy ready / busy ready / busy data cache ready / busy : '0' ready : '1' 7 write protect write protect write protect write protect write protect protected : '0' not protected : ' 1 ' parameter symbol device identifier byte description 1 st manufacturer code 2 nd device identifier 3 rd internal chip number, cell type, number of simultaneously programmed pages, interleaved program, write cache. 4 th page size, block size, redundant area size 5 th plane number, ecc level 6 th technology (design rule), edo, interface http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 22 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.10. read id data table 2.10.1. 3 rd byte of device identifier description part number voltage bus width manufacture code device code 3 rd 4 th 5 th 6 th H27UCG8T2Myr-bc 3.3v x8 adh deh 94h d2h 04h 43h 3 rd cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 internal chip number 1 2 4 reserved 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 number of simultaneously programmed pages 1 2 4 8 0 0 1 1 0 1 0 1 interleaved program between multiple dice not support support 0 1 write cache not support support 0 1 http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 23 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.10.2. 4 th byte of device id entifier description 2.10.3. 5 th byte of device id entifier description 4 th cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 page size (without spare area) 2kb 4kb 8kb reserved 0 0 1 1 0 1 0 1 block size (without spare area) 128kb 256kb 512kb 768kb 1mb 2mb reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 redundant area size 128b 224b 448b reserved reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 5 th cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 plane number 1 2 4 8 0 0 1 1 0 1 0 1 ecc level 1bit/512bytes 2bit/512bytes 4bit/512bytes 8bit/512bytes 16bit/512bytes 24bit/2048bytes 24bit/1024bytes reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 reserved 0 0 0 http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 24 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 2.10.4. 6 th byte of device identifier description 6 th cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 nand technology 48nm 41nm 32nm reserved reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 edo support not support support 0 1 nand interface sdr ddr 0 1 reserved 0 0 0 http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 25 H27UCG8T2M series 64gb (8192m x 8bit) nand flash cl s cs wp command cle ce# we# ale i/ox dh ds als clh ch : dont care tt t t t t t t alh t 3. timing diagram bus operation there are six standard bus operations th at control the device. these are command input, address in put, data input, data output, write protect, and standby. 3.1. command latch cycle timings figure 5. command latch timings note: all command except reset, read status, and multi plane read status is issued to command register on the rising edge of we#, when cle is high, ce# and ale is low, and device is not busy state http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 26 H27UCG8T2M series 64gb (8192m x 8bit) nand flash wc clh ch wp wh din 1 din final dh dh dh ds ds ds wp wp cle ale ce# i/ox we# als din 0 t t t t t t t t t t t t t t : dont care tcls tcs twc tals tals tals tals tals talh talh talh talh talh twc twc twc twp twp twh twp twp twh twh twh tds col.add1 cle ce we ale i/ox col.add2 row add1 row add2 row add3 tds tds tds tds tdh tdh tdh tdh tdh : dont care 3.2. address latch cycle timings figure 6. address latch timings 3.3. input data latch cycle timings figure 7. input data cycle timings note: data input cycle is accepted to data register on the rising edge of we#, when cle and ce# and ale are low, and device is not busy state. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 27 H27UCG8T2M series 64gb (8192m x 8bit) nand flash rr chz rhz rhoh dout ce# re# i/ox r/b# rea dout rloh rea rp reh rc t t t t t t t t t t : dont care cr t reh rea rc rr chz rhz rhoh dout dout ce# re# i/ox r/b# dout rea rhz rea t t t t t t t t t t 3.4. data output cycle timings (cle=l, we#=h, ale=l, wp#=h) figure 8. data output cycle timings notes: 1. transition is measured +/-200mv from steady state voltage with load. this parameter is sampled and not 100% tested. ( t chz , t rhz ) 2. t rloh is valid when frequency is higher than 10 mhz. t rhoh starts to be valid when frequency is lower than 10 mhz. 3.5. data output cycle timings (edo type, cle=l, we#=h, ale=l) figure 9. data output cycle timings (edo) notes: 1. transition is measured +/-200mv from steady state voltage with load. this parameter is sampled and not 100% tested. ( t chz , t rhz ) 2. t rloh is valid when frequency is higher than 10 mhz. t rhoh starts to be valid when frequency is lower than 10 mhz. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 28 H27UCG8T2M series 64gb (8192m x 8bit) nand flash t cls t clh t cs t wp t ch t cr t chz t coh t whr t alh t ar t rea t rhz t rhoh t ds t dh t alh t als wc t wp t wh t : dont care cle ce# we# ale re# i/ox 78h row.add1 row.add2 row.add3 status cle ce# re# i/ox we# 70h status output cls t clh t cs t clr t ch t cr t chz t rhz t rhoh t wp t whr t ds t dh t ir t rea t : dont care 3.6. read status cycle timings figure 10. read status timings 3.7. multi plane read status timings figure 11. multi plane read status timings http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 29 H27UCG8T2M series 64gb (8192m x 8bit) nand flash ce# cle ale we# re# i/ox 00h col. add1 col. add2 row. add1 row. add2 row. add3 30h dout n dout n+1 dout n+2 r/b# t ar t rc t r t wb t rr t wc : dont care t rhz dout m ce# cle ale we# re# i/ox 00h col. add1 col. add2 row. add1 row. add2 row. add3 30h dout n dout n+1 dout n+2 r/b# t ar t rc t r t wb t rr t wc : dont care t clr t chz t coh t cs t ch t cls t clh 3.8. page read operation timings (read one page) figure 12. page read operation timings 3.9. page read operation timings (intercepted by ce#) figure 13. page read operation timings http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 30 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.10. page read operation timings with ce# don't care figure 14. page read operation timings with ce# don't care 3.11. random data output timings figure 15. random data output timings note: random data output is available within a page. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 31 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.12. multi plane page read operation with random data output timings figure 16. multi plane page read operation timings with random data output notes: 1. multi plane page addresses are required to be the same. 2. multi plane random data-out must be used after multi plane read operations. 3. multi plane page read must be used after multi plane programmed page, multi plane cache program, and multi plane copy-back program. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 32 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.13. cache read operation timings figure 17. cache read operation timings notes: 1. the column address will be rese t to 0 by the 31h/3fh command input. 2. cache read operation is available only within a block. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 33 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.14. multi plane cache read operation timings figure 18. multi plane cache read operation timings notes: 1. the column address will be reset to 0 by the 31h/3fh command input. 2. cache read operation is available only within a block. 3. make sure to terminate the operation with 3fh command. if the page read operation is completed, issue ffh reset before next operation. 4. multi plane page addresses are required to be the same. 5. multi plane cache read must be used after multi plane programmed page, multi plane cache program, and multi plane copy-back program http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 34 H27UCG8T2M series 64gb (8192m x 8bit) nand flash device code 3rd cyc. 4th cyc. 90h ce# cle we# ale re# i/ox 00h adh ar whr rea 5th cyc. 6th cyc. maker code t t t 3.15. read id operation timings figure 19. read id operation timings 3.16. page program operation timings figure 20. page program operation timings note: t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 35 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.17. page program operation timings with ce# don't care figure 21. page program operation timings with ce# don't care note: t adl is the time from the we# rising edge of final addr ess cycle to the we# rising edge of first data cycle. 3.18. random data input timings figure 22. random data input timings notes: 1. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. 2. random data input can be performed in a page. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 36 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.19. multi plane page program operation timings figure 23. multi plane page program operation timing notes: 1. any command between 11h and 81h is prohibited except 70h, 78h, 75h and ffh 2. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. 3. multi plane page addresses are required to be the same. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 37 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.20. copy-back program operation timings with random date input figure 24. copyback program operation timing with random data input note: copy back operation is allowed only within the same memory plane. 3.21. cache program operation timings figure 25. cache program operation timings note: t prog = program time for the last page + program time for the (last -1)th page - (command input cycle time + address input cycle time + last page data loading time http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 38 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.22. multi plane cache program operation timings figure 26. multi plane cache program operation timings notes: 1. t prog = program time for the last page + program time for the (last -1)th page - (command input cycle time + address input cycle time + last page data loading time) 2. make sure to terminate the operation with 80h-10h- command sequence. if the operation is terminated by 80h-15h command sequences, monitor i/o5 (ready/busy) and i/o6 (data cache ready/busy) by issuing read status command (70h) and make sure the previous and current cache page program operation is completed. if the page program operation is completed, issue ffh reset before next operation. 3. selected page address except a22 within two blocks must be same. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 39 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3.23. block erase operation timings figure 27. block erase operation timings 3.24. multi plane erase operation timings figure 28. multi plane erase operation timings http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 40 H27UCG8T2M series 64gb (8192m x 8bit) nand flash ffh t rst ce# cle we# i/ox r/b# t wb 3.25. reset timings figure 29. reset timings http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 41 H27UCG8T2M series 64gb (8192m x 8bit) nand flash cle ale ce# i/ox we# r/b# re# 00h address (5 cycle) 30h data output (serial access) t r 4. device operation 4.1. page read this operation is initialized by 00h-30h to the command regi ster along with followed by five address input cycles. the 8,640 bytes of data within the selected page are transferred to the data registers in less than 200 ? (t r ). the system controller may detect the completion of this data transfer 200 ? (t r ) by analyzing the output of r/b# pin. once the data in a page is loaded into the data registers, they may be read out in 25 ? cycle time by sequentially pulsing re#. the repetitive high to low transitions of the re# clock make the device output the data starting from the selected col - umn address up to the last column address. the device may output random data in a page instead of th e consecutive sequential data by writing random data out - put command. the column address of next data, which is going to be out, may be changed to the address, which fol - lows random data output command. rand om data output can be operated multiple times, regardless of how many times it is done in a page. figure 30. page read random data output random data output operation changes the column address from which data is being read in the page register. ran - dom data output only is issued in ready state. refer to figure 3 1 . http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 42 H27UCG8T2M series 64gb (8192m x 8bit) nand flash i/ox r/b# re# 00h data t r output address (5 cycle) 30h data output 05h address (2 cycle) e0h 30h 31h d0 ... dn 31h d0 ... dn 3fh d0 ... dn cle we# re# i/ox r/b# as defined for read t r t cbsyr column 0 t cbsyr column 0 t cbsyr column 0 figure 31. random data output 4.2. cache read (available only within a block) to improve page read throughput, cache read operation is used within a block. first step is same as normal page read, issuing a page read sequence (00-30h). after random access (r/b# returns to high), 31h command is latched into the com- mand register. data is being transferred from the data register to the cache register. while cache register data is outputted, next page is transferred from memory cell to data register. r/b# will stay low during present page random accessing and previous page transferring to cache register. because it is no t necessary to output a whole page data before issuing another 31h command, if serial da ta output time exceeds random access time (t r ), the random access time can be hidden. the sub- sequent pages are issued additional 31h commands. to terminate cache read, 3fh command should be issued. this com- mand transfer data from data register to the cache register without issuing next page read. during the cache read opera- tion, device doesn?t allow any other command except cache read command (31h), read status (70h, 78h, 75h), read (00h), and reset (ffh). to carry out other operations after cache operation, cache read must be ended by 3fh command or issue reset (ffh) before next operation. figure 32. cache read http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 43 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address : valid address (3 cycle) 60h 30h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : fixed low page address : page m plane address : fixed high block address : block k column address : valid 00h address (5 cycle) address (2 cycle) 05h e0h data output 4.3. cache read enhanced (available only within a block) this command extends the cache read command. while, by issuing a cache read command, the next page address of the next page is automatically incremented by 1, the next page address of the next page is given arbitrarily by the user. the cache read enhanced command sequence consists of a 00h command, five address cycles and a 31h command, which replaces the single 31h command of the cache read command sequence. 4.4. multi plane page read multi-plane page read is an extension of page read, for a single plane with 8,640byte page registers. since the device is equipped with two memory planes, activating the two sets of 8,640byte page resisters enables a random read of two pages. multi-plane page read is initiated by repeating command 60h followed by three address cycles twice. in this case, only same page of each block can be selected from each plane. after read confirm command (30h) the 17,280bytes of data within the selected two pages are transferred to the data registers in less than 200 ? (t r ). the system controller can detect the completion of data transfer (t r ) by monitoring the output of r/b# pin. once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with five address cycles, command 05h wi th two column address and finally e0h. the data output of second plane can be read out using the identical command sequences. the restrictions for multi-plane page read are shown in figure 33. multi-plane page read must be used in the block which has been programmed with multi-plane page program. figure 33. multi plane page read http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 44 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address : valid address (3 cycle) 60h 33h page address : page m plane address : fixed high block address : block k b t cbsyr i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : fixed low page address : page m plane address : fixed high block address : block k column address : valid 00h address (5 cycle) address (2 cycle) 05h e0h data output 31h 4.5. multi plane cache read (available only within a block) the device supports multi-plane cache read, which enables high read throughput by reading two pages in parallel. figure 34 shows the command sequence for the multi-plane cache read operation. both confirm commands, 30h and 33h, are valid for the first page read sequence. figure 34. multi plane cache read notes: 1. plane 0 and plane 1 should be selected within the same chip 2. only one block should be selected from the each plane. 3. multi plane cache read is available only within a block per plane. 4. selected page address except a22 within two blocks must be same. 5. the operation has to be terminated with ?3fh? command. 4.6. multi plane cache read enhanced (available only within a block) this command is a multi-plane extension of the cache read enhanced command. 4.7. read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad- dress input of 00h. six read cycles sequentially output the manufacturer code (adh), and the device code and 3rd, 4th, 5th, 6th cycle id, respectively. the command register remains in read id mode until further commands are issued to it. figure 35 shows the operation sequence, while 2.10 read id data tables explain the byte meaning. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 45 H27UCG8T2M series 64gb (8192m x 8bit) nand flash cle ale we# re# i/ox 78h row.add1 row.add3 row.add2 status 70h status cle we# re# i/ox 90h cle we# ale re# i/ox 00h adh de 04 43 d2 whr 94h t figure 35. read id 4.8. read status register the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. after writing read status (70h) or multi plane read status (78h,75h) command to the command register, a read cycle outputs the content of the status register to the i/o pins only if ce# and re# are low, whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections ev en when r/b# pins are common-wired. refer to 2.8. status register codings for specific status register definitions and figure 36, figure 37 for read status. the command reg- ister remains in read status mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. figure 36. read status figure 37. multi plane read status http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 46 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 80h address 5 cycle data input status 70h 10h cle prog t i/o 0 = 0 program pass i/o 0 = 1 program fail ce# ale we# re# i/ox r/b# 4.9. page program the device is programmed as a page unit. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 times. the program addressing should be done in sequential order in a block. a page program cycle consists of a serial data loading period in which up to 8,640bytes of data may be loaded into the data register, followed by a no n-volatile programming period where the loaded data is pro- grammed into the appropriate cell. the serial data-loading period begins by inputting the serial data input command (80h), followed by the five cycle address inputs and then serial data. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows rand om data input command (85h). random data input may be operated multiple times, regardless of how many times it is done in a page. the page program confirm command (10h) initiates the programming process. writing 10h alone without previously entering th e serial data will not initiate the pro- gramming process. the internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b# output, or the status bit (i/ o6) of the status register. only the read status command and reset command are valid while programming is in progress. the write status bit (i/o 0) is valid, when all internal operations are complete (status bit i/o 6 = high). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the command register. figure 38 and figure 39 details the sequence. figure 38. page program figure 39. random data input i/ox r/b# column address 80h address (5 cycle) address (2 cycle) data input 85h data input 70h status 10h prog t http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 47 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 80h address (5 cycle) 11h t dbsy data input a 81h address (5 cycle) 10h t prog data input i/ox r/b# 70h status 1 plane address st 2 plane address nd a i/ox r/b# 4.10. multi plane program device supports multiple plane program. it is possible to program in parallel 2 pages, one per each plane. a multiple plane program cycle consists of a double serial data loading period in which up to 17,280bytes of data may be loaded into the data register, foll owed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period be gins by inputting the serial data input command (80h), fol- lowed by the five cycle address inputs and then serial data for the 1st page. address for this page must be within first plane (a<22>=0). the data of first page other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program operation. the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (t dbsy ). once it has become ready again, 81h command must be issued, followed by second page address (5 cycles) and its serial data input. address for this page must be within second plane (a<22>=1). the data of second page other than those to be programmed do not need to be loaded. program confirm command (10h) makes parallel programming of both pages start. user can check oper- ation status by r/b# pin or read status register command, as if it were a normal page program; status register command is also available during dummy busy time (t dbsy ). in case of fail in first plane or second plane page program, fail bit of status register will be set: pass/fail status of each plane can be checked by multi plane read status. figure 40 details the sequence. figure 40. multi plane page program notes: 1. plane 0 and plane 1 should be selected within the same chip 2. only one block should be selected from the each plane. 3. selected page address except for a22 within two blocks must be same. 4. any command between 11h and 81h is prohibited except 70h/78h/75h and ffh. 5. read status command can be 70h or 78h or 75h. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 48 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 4.11. cache program (available only within a block) cache program is an extension of the standard page program, which is executed with 8,640 bytes cache registers and same bytes data register. after the serial data input command (80h) is loaded to the command register, followed by 5 cycles of address, a full or partial page of data is latc hed into the cache register, and then the cache write command (15h) is loaded to the command register. after that sequence, the data in the cach e register is transferred into the data register for cell programming. at this time, the device remains in busy state. after all data of the cache register is trans- ferred into the data register, the device go es to the ready state to load the next data into the cache register by issuing another cache program command sequence (80h-15h). there are some restrictions for cache program operation. 1. the cache program command is available only within a block. 2. user must give address and data after 80h command. the busy time of first sequence equals the time it takes to tr ansfer the data of cache regist er to the data register. cell programming of the data of data register and loading of the next data into the cache register is consequently processed as a pipeline method. on the second and cascading sequence, transfer from the cache register to the data register is held off until cell programming of current data register contents has been done. read status command (70h) may be issued to find out when the cache register is ready by polling the cache-busy sta- tus bit (i/o 6). in addition, the status bit (i/o 5) can be used to determine when the cell programming of the current data register contents is complete. pass/fail status of only the previous page (i/o 1) is available upon the return to ready state. if the system monitors the progress of programming only with r/b#, the last page of the target programming sequence must be programmed with actual page program command (10h). if the cache program command (15h) is used instead, status bit (i/o5) must be polled to find out when the last programming is actually finished before starting other opera- tions such as read. pass/fail status is available in two steps. i/o 1 returns with the status of the previous page upon ready or i/o6 status bit changing to "1", and later i/o 0 wi th the status of current page upon true ready (returning from internal programming) or i/o 5 status bit changing to "1". i/o 1 may be read together when i/o 0 is checked. refer to 2.8. status register coding and figure 41 for more details. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 49 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 80h address (5 cycle) 15h t cbsyw data input a 80h address (5 cycle) 15h t cbsyw data input b i/ox r/b# 80h address (5 cycle) 10h t prog data input i/ox r/b# 70h status a b i/ox r/b# r/b# pin data cache ready /bysy (i/o6) i/o 1 => i/o 0 => invalid invalid page1 invalid page1 page2 page n-2 invalid invalid invalid page n-1 page n data cache ready /bysy (i/o5) 70h sr out 70h sr out 80h-add-data-15h 80h-add-data-15h 70h sr out 80h-add-data-15h 70h sr out 80h-add-data-15h 70h sr out 70h sr out page 1 page 2 page n-1 page n page 1 page 2 page n-1 page n during both i/o6 and i/o5 return to high, the pass/fail for previous page and current page can be shown through i/o1 and i/o0 concurrently. prog t cbsyw t cbsyw t cbsyw t pass / fail status for each page programmed by the cache program operation can be detected by the read status operation. i/o 0 : pass / fail of the current page program operation. i/o 1 : pass / fail of the previous page program operation. the pass / fail status on i/o 0 and i/o 1 are valid under the following conditions. status on i/o 0 : ready / busy is ready state. the ready/ busy is output on i/o 5 by read status operation or r/b pin after the 10h command. status on i/o 1 : data cache ready / busy is ready state. the data cache ready / busy is output on i/o 6 by read status operation or r/b pin after the 15h command. figure 41. cache program http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 50 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 4.12. multi plane cache program (available only within a block) the device supports multi plane cache program, which enab les high program throughput by programming two pages. the serial data-loading period begins by inputting the se rial data input command (80h), followed by the five cycle address inputs and then serial data for the first page. addr ess for this page must be within first plane (a<22>=0). the data of first page other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program operation. the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (t dbsy ). once it has become ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. address for this page must be within second plane (a<22>=1). the data of second page other than th ose to be programmed do not need to be loaded. cache program confirm command (15h) makes parallel programming of both pages start. and last page inputs program confirm command (10h). the last page of the target programming sequence must be programmed with actual page program command (10h). if the operation is terminated, issue ffh reset before next operation. if multiplane cache program begins, multiplane sequence should be used until multiplane cache program is ended. figure 44 shows the command sequence for multi plane cache program operation. after the "15h"or"10h" command, the result per plane of the operation is shown through the "78h" multi plane read status command. figure 42. multi plane cache program notes: 1. plane 0 and plane 1 should be selected within the same chip 2. only one block should be selected from the each plane. 3. multi plane cache program is available only within a block per plane. 4. selected page address except for a22 within two blocks must be same. 5. the operation has to be terminated with ?10h? command.? 6. any command between 11h and 81h is prohibited except 70h/78h/75h and ffh. 7. read status command can be 70h or 78h or 75h. reading the status per plane is available only 78h. 80h t cbsyw a 80h 81h i/ox r/b# a address (5 cycle) data input 11h address (5 cycle) data input 11h 81h address (5 cycle) data input 15h t dbsy address (5 cycle) data input 10h 78h address (3 cycle) status per plane column address : valid page address : page m plane address : fixed low block address : block j column address : valid page address : page m plane address : fixed high block address : block k column address : valid page address : page m+n plane address : fixed low block address : block j column address : valid page address : page m+n plane address : fixed high block address : block k i/ox r/b# t prog t dbsy http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 51 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 4.13. copy-back program copy-back program with read for copy-back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit e rror is not in data stored. since the time-consuming re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned free block. copy-back operation is a sequential exe - cution of read for copy-back and of copy-back program wi th the destination page address. a read operation with "35h" command and the address of the source page moves th e whole 8,640-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore, copy-back program operation is initiated by issuing page-copy data-input command (85h) with destination page address. actual programming operation begins after program confirm command (10h) is issued. once the program process starts, the read status re gister command (70h) may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b# output, or the status bit (i/o 6) of the status register. when the copy-b ack program is complete, the write status bit (i/o 0) may be checked. the command register remains in read status command mode until another valid command is written to the command register. during copy-back program, data modification is possible using random data input command (85h) as shown in figure 43. figure 43. copyback program 00h address (5 cycle) 35h data output t r 85h address (5 cycle) data t prog i/ox r/b# target address 85h address (2 cycle) data 10h 70h status column address 1,2 i/ox r/b# source address a a http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 52 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address 1,2 : valid address (3 cycle) 60h 35h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : valid page address : page n plane address : fixed low block address : block p column address 1,2 : valid c 85h address (5 cycle) address (2 cycle) data 11h i/ox r/b# d column address 1,2 : valid 81h address (5 cycle) data 10h data 85h address (2 cycle) 85h data t prog i/ox r/b# c column address : fixed low page address : page m plane address : fixed high block address : block k column address 1,2 : valid d 00h address (5 cycle) address (2 cycle) 05h e0h data output column address : valid page address : page n plane address : fixed high block address : block q t dbsy 4.14. multi plane copy-back program multi-plane copy-back program is an extension of copy-back program, for a single plane with 8,640 byte page registers. since the device is equipped with two memory planes, activating the two sets of 8,640-byte page registers enables a si- multaneous programming of two pages. figure 44 and figu re 45 show command sequence for the multi-plane copy-back operation. first case, figure 44, shows random data input of two planes that started right after finishing random data out- put of previous two planes. second case, figure 45, shows the random data input of each plane which started right after finishing the random data output of each plane. figure 44. multi plane copyback program http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 53 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address 1,2 : valid address (3 cycle) 60h 35h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : valid page address : page m plane address : fixed low block address : block p column address 1,2 : valid c 85h address (5 cycle) address (2 cycle) data data i/ox r/b# c column address : fixed low page address : page m plane address : fixed high block address : block k column address 1,2 : valid d 00h address (5 cycle) address (2 cycle) i/ox r/b# d column address : valid page address : page m plane address : fixed high block address : block q column address 1,2 : valid 81h address (5 cycle) data 10h e0h 05h address (2 cycle) 85h data t prog 85h 11h t dbsy data output figure 45. multi plane copyback program 4.15. block erase the erase operation is done on a block basis. block address lo ading is accomplished in two cycles initiated by an erase setup command (60h). only address a22 to a33 is valid while a14 to a21 is ignored. the erase confirm command (d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we# after the erase confirm command input, the internal write controller handles erase and erase verify. once the erase process starts, the read status register command may be entered to read the status register. the system controller can detect the completion of an erase by monitoring the r/b# output, or the status bit (i/o 6) of the status register. only the read status command and reset command ar e valid while erasing is in progress. when the erase op- eration is completed, the write status bit (i/o 0) may be checked. figure 46 details the sequence. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 54 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 60h 70h address (3 cycle) d0h status t bers i/ox r/b# row add 1,2,3 60h 70h address (3 cycle) 60h status t bers address (3 cycle) d0h page address : fixed low plane address : fixed low block address : block n i/ox r/b# page address : fixed low plane address : fixed high block address : block m figure 46. block erase 4.16. multi plane block erase. multiple plane erase, allows parallel erase of two blocks, one per each memory plane. block erase setup command (60h) must be repeated two times, each time followed by first block and second block ad- dress respectively (3 cycles each). as for block erase, d0h command makes embedded operation start. multi plane erase does not need any dummy busy time between first and second block address insertion. address limitation required for multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for multiple plane program. refer to the detail sequence as shown below. figure 47. multi plane block erase 4.17. reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value e0h when wp# is high. refer to 2.8. status register coding for device status after reset operation. if the device is already in reset state, the command reg- ister will not accept a new reset command. the r/b# pin goes low for t rst after the reset command is written. refer to figure 48. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 55 H27UCG8T2M series 64gb (8192m x 8bit) nand flash i/ox r/b# ffh rst t figure 48. reset http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 56 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 3v device = 2.7v t cs ffh 2.7v 1 (max) ms 10 (max) 50 (min) 2 (max) ms vcc ramp starts : dont care : undefined vcc 0v ce# wp# cle we# ale re# i/ox r/b# 5. other features 5.1. data protection & power on/off sequence the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal volt- age detector disables all functions whenever v cc is below about 2.0v (3.3v device). wp# pin provides hardware pro- tection and is recommended to be kept at v il during power-up and power-down. the reset command (ffh) must be issued to all dies as the first command after device is power up. each r/b# will be busy for maximum of 2ms after reset command is issued. in this time, the acceptable command is 70h or 78h or 75h. figure 49. data protection and power on / off http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 57 H27UCG8T2M series 64gb (8192m x 8bit) nand flash rp value guidence rp (min) = = where il is the sum of the input current of all devices tied to the r/b# pin. rp(max) is determined by maximum permissible limit of tr @ vcc = 3.3v, ta = 25c, c l =50pf fig. rp vs tr, tf & rp vs ibusy vcc (max.) - v ol (max.) 3.2v p$?, l i ol + ?, l rp ibusy rp (ohm) ibusy ibusy [a] tr, tf [s] tf 3.3 381 290 1.65 96 189 1.1 0.825 4.2 4.2 4.2 4.2 busy ready vcc v oh tr tf v ol v ol : 0.4v, v oh : 2.4v vcc 300n 3m 1k 2k 3k 4k 200n 2m 100n 1m gnd device open drain output r/b# 5.2. ready / busy the device has a ready/busy output that provides method of indicating the completion of a page program, erase, copy- back and random read completion. the r/b# pin is normally high and goes to low when the device is busy (after a reset, read, program, and erase operation). it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/b# outputs to be or-tied. because pull-up resistor value is re- lated to t r (r/b#) and current drain during busy (i busy ), an appropriate value can be obtained with the following refer- ence chart (figure 50). its value can be determined by the following guidance. figure 50. ready / busy http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 58 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 80h 10h we# i/ox wp# r/b# ww t 80h 10h we# i/ox wp# r/b# ww t 60h d0h we# i/ox wp# r/b# ww t 60h d0h we# i/ox wp# r/b# ww t 5.3. write protect operation the erase and program operations are automatically reset when wp# goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 51 ~ 64). figure 51. enable programming figure 54. disable erasing figure 52. disable programming figure 53. enable erasing http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 59 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 6. application notes and comments 6.1. paired page address information paired page address paired page address 0415 2839 6c7d a10b11 e14f15 12 18 13 19 16 1c 17 1d 1a 20 1b 21 1e 24 1f 25 22 28 23 29 26 2c 27 2d 2a 30 2b 31 2e 34 2f 35 32 38 33 39 36 3c 37 3d 3a 40 3b 41 3e 44 3f 45 42 48 43 49 46 4c 47 4d 4a 50 4b 51 4e 54 4f 55 52 58 53 59 56 5c 57 5d 5a 60 5b 61 5e 64 5f 65 62 68 63 69 66 6c 67 6d 6a 70 6b 71 6e 74 6f 75 72 78 73 79 76 7c 77 7d 7a 80 7b 81 7e 84 7f 85 82 88 83 89 86 8c 87 8d 8a 90 8b 91 8e 94 8f 95 92 98 93 99 http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 60 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 96 9c 97 9d 9a a0 9b a1 9e a4 9f a5 a2 a8 a3 a9 a6 ac a7 ad aa b0 ab b1 ae b4 af b5 b2 b8 b3 b9 b6 bc b7 bd ba c0 bb c1 be c4 bf c5 c2 c8 c3 c9 c6 cc c7 cd ca d0 cb d1 ce d4 cf d5 d2 d8 d3 d9 d6 dc d7 dd da e0 db e1 de e4 df e5 e2 e8 e3 e9 e6 ec e7 ed ea f0 eb f1 ee f4 ef f5 f2 f8 f3 f9 f6 fc f7 fd fa fe fb ff when program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also a coupled row paired page data may be damaged. for example, during page program operation of page address 05h is aborted by reset or power down, the data of 00h, 01h, 04h, and 05h page address may be spoiled. http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 61 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 6.2. acceptable command after 80h after program start command (80h) is inputted, do not input any command except 85h, 10h, 11h, 15h, and ffh. if a command is inputted except these commands, the program operation cannot be executed. 6.3. acceptable command between start command and confirm command only reset command is available between start commands and confirm commands set (start command-address-confirm command style) that is mentioned in 1.7 command set. if other command is inputted, the operation cannot be executed. do not input any commands except ffh. for instance, it is impossible to perform a normal page read operation, if any command is inputted between page read command set (00h - 5 address cycle - 30h). 6.4. restriction of read status value in multi plane operation during multi plane operation, only 70h, 78h,75h and ffh are available between 11h-81h. but, the pass/fail output infor- mation of 70h and 78h and 75h is not valid. during this time , only ready / busy (i/o6 and i/o5) state can be checked. refer to figure 55. figure 55. restriction read status in multi plane operation 6.5. page program failure if the page program operation for page address n is fail, remain data in data register may be different to input data by host. therefore, do not attempt to program the page addres s n in another block without the data input sequence. the same input sequence of 80h command, address and data is necessary. 6.6. restriction multi plane operation to prevent abnormal multi plane operation, do not input bad block address to all multi plane operation. otherwise, the input data of valid block could be lost and the operation could be abnormally stopped. 80h i/ox r/b# address data i/o6 => i/o5 => i/o1 => i/o0 => valid invalid invalid invalid 11h 70h sr out 81h address data 10h 70h sr out valid invalid invalid invalid valid invalid invalid valid 70h sr out t prog t dbsy io 0 = 0, pass io 0 = 1, fail http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 62 H27UCG8T2M series 64gb (8192m x 8bit) nand flash 7. hynix nand flash part number no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1ce,sdp h 2 7 u c g 8 t 2 m y r - b x no. code description 1 hynix h : hynix 2 product family 2 : flash 3 product mode 7 : nand flash 4 power supply u : 2.7~3.6v l : 2.7v s : 1.8v / 1.8v j : 2.7~3.6v / 1.2v q : 2.7~3.6v / 1.8v 5,6 density 64 : 64mb 12 : 128mb 25 : 256mb 51 : 512mb 1g : 1gb 2g : 2gb 4g : 4gb 8g : 8gb ag : 16gb bg : 32gb cg : 64gb dg : 128gb eg : 256gb fg : 512gb 1t : 1tb 2t : 2tb pg : 192gb rg : 384gb vg : 768gb 7 organization 8 : x8 6 : x16 8 nand classification s : slc + single die + small block a : slc + double die + small block b : slc + quadruple die + small block f : slc + single die + large block g : slc + double die + large block h : slc + quadruple die + large block j : slc + odp + large block k : slc + dsp + large block t : mlc + single die + large block u : mlc + double die + large block v : mlc + quadruple die + large block w : mlc + dsp + large block y : mlc + odp + large block r : mlc + 6die + large block z : mlc + 12die + large block c : mlc + 16die + large block m : tlc + sdp + large block n : tlc + ddp + large block p : tlc + qdp + large block q : tlc + odp + large block http://www..net/ datasheet pdf - http://www..net/
rev 1.0 / aug. 2010 63 H27UCG8T2M series 64gb (8192m x 8bit) nand flash note - capital letter : fixed item - small letter : non-fixed item 9 function mode 1 : 1ce & 1r/b, sequential row read enable 2 : 1ce & 1r/b, sequential row read disable 4 : 2ce & 2r/b, sequential row read enable 5 : 2ce & 2r/b, sequential row read disable f : 4ce & 4r/b, sequential row read disable t: 5ce & 5r/b, sequential row read disable u: 6ce & 6r/b, sequential row read disable v: 8ce & 8r/b, sequential row read disable d : 2ce&2r/b, dual interface 10 generation m : 1st generation b : 3rd generation d : 5th generation a : 2nd generation c : 4th generation e : 6th generation 11 package type t : tsop1 v : wsop s : usop n : lsop f : fbga-63(9x11x1.0) i : vfbga-100(12x18x1.0) j : lfbga-100(12x18x1.4) x : llga (14x18-1.47t) y : vlga (14x18-1.0t) m : wlga (14x18-0.75t) u : ulga (12x17-0.75t) h : xlga (10x7.5) w : wafer c : pgd1 (chip) d : pgd2 k : kgd 12 package material a : wafer p : lead free l : leaded r : lead & halogen free 13 - - 14 bad block b : included bad block p : all good block s : 1~5 bad block included 15 temperature c : 0 ~ 70 c m : -30 ~ 85 c e : -25 ~ 85 c i : -40 ~ 85 c http://www..net/ datasheet pdf - http://www..net/

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